1. Field of the Invention
The present invention relates generally to the field of semiconductor devices. More particularly, the present invention relates to a memory cell array with hierarchical bit line structure.
2. Description of the Prior Art
Hierarchical bit line architecture has been applied to achieve high-speed operation. For example, U.S. Pat. No. 6,456,521 to Hsu et al. discloses a hierarchical bit line DRAM architecture system having a DRAM array which includes master and local bit lines, wherein each master bit line couples to two local bit lines.
U.S. Pat. No. 6,084,816 discloses a memory cell array divided into an odd number of sub-arrays. U.S. Pat. No. 6,084,816 further discloses word lines comprising an upper word line portion with low resistivity arranged in parallel with a lower word line portion which forms the gate of the cell transistor.